vishay siliconix si5908dc document number: 73074 s10-0548-rev. b, 08-mar-10 www.vishay.com 1 dual n-channel 20 v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? power mosfets ? ultra low r ds(on) and excellent power handling in compact footprint ? compliant to rohs directive 2002/95/ec applications ? load switch ? pa switch ? battery switch product summary v ds (v) r ds(on) ( )i d (a) 20 0.040 at v gs = 4.5 v 5.9 0.045 at v gs = 2.5 v 5.6 0.052 at v gs = 1.8 v 5.2 bottom view 1206-8 chipfet ? s 1 g 1 s 2 g 2 d 1 d 1 d 2 d 2 1 marking code cc xxx lot traceability and date code part # code ordering information: SI5908DC-T1-E3 (lead (pb)-free) si5908dc-t1-ge3 (lead (pb)-free and halogen-free) d 1 g 1 s 1 n-channel n-channel mosfet d 2 g 2 s 2 mosfe t notes: a. surface mounted on 1" x 1" fr4 board. b. see reliability manual for profile. the chipfet is a leadless package. the end of t he lead terminal is exposed copper (not p lated) as a result of the singulation process in manufacturing. a solder fillet at the exposed copper tip cannot be guarant eed and is not required to ensure adequate bottom side solder interconnection. c. rework conditions: manual soldering with a sol dering iron is not recommended for leadless components. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol 5 s steady state unit drain-source voltage v ds 20 v gate-source voltage v gs 8 continuous drain current (t j = 150 c) a t a = 25 c i d 5.9 4.4 a t a = 85 c 4.2 3.1 pulsed drain current i dm 20 continuous source current (diode conduction) a i s 1.8 0.9 maximum power dissipation a t a = 25 c p d 2.1 1.1 w t a = 85 c 1.1 0.6 operating junction and storage temperature range t j , t stg - 55 to 150 c soldering recommendations (peak temperature) b, c 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a t 5 s r thja 50 60 c/w steady state 90 110 maximum junction-to-foot (drain) steady state r thjf 30 40
www.vishay.com 2 document number: 73074 s10-0548-rev. b, 08-mar-10 vishay siliconix si5908dc notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not subject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. typical characteristics 25 c unless otherwise noted specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.4 1.0 v gate-body leakage i gss v ds = 0 v, v gs = 8 v 100 na zero gate voltage drain current i dss v ds = 20 v, v gs = 0 v 1 a v ds = 20 v, v gs = 0 v, t j = 85 c 5 on-state drain current a i d(on) v ds 5 v, v gs = 4.5 v 20 a drain-source on-state resistance a r ds(on) v gs = 4.5 v, i d = 4.4 a 0.032 0.040 v gs = 2.5 v, i d = 4.1 a 0.036 0.045 v gs = 1.8 v, i d = 1.9 a 0.042 0.052 forward transconductance a g fs v ds = 10 v, i d = 4.4 a 22 s diode forward voltage a v sd i s = 0.9 a, v gs = 0 v 0.8 1.2 v dynamic b total gate charge q g n-channel v ds = 10 v, v gs = 4.5 v, i d = 4.4 a 57.5 nc gate-source charge q gs 0.85 gate-drain charge q gd 1 gate resistance r g 1.9 tu r n - o n d e l ay t i m e t d(on) n-channel v dd = 10 v, r l = 10 i d ? 1 a, v gen = 4.5 v, r g = 6 20 30 ns rise time t r 36 55 turn-off delay time t d(off) 30 45 fall time t f 12 20 source-drain reverse recovery time t rr i f = 0.9 a, di/dt = 100 a/s 45 90 output characteristics 0 4 8 12 16 20 012345 v gs = 5 v thru 2 v v ds - drain-to-source voltage (v) - drain current (a) i d 1v 1.5 v transfer characteristics 0 4 8 12 16 20 0.0 0.4 0.8 1.2 1.6 2.0 t c = - 55 c 125 c 25 c v gs - gate-to-source voltage (v) - drain current (a) i d
document number: 73074 s10-0548-rev. b, 08-mar-10 www.vishay.com 3 vishay siliconix si5908dc typical characteristics 25 c, unless otherwise noted on-resistance vs. drain current gate charge source-drain diode forward voltage - on-resistance ( ) r ds(on) 0.00 0.02 0.04 0.06 0.08 0.10 048121620 i d - drain current (a) v gs =1.8v v gs = 4.5 v v gs =2.5v 0 1 2 3 4 5 0123456 v ds =10v i d =4.4a - gate-to-source voltage (v) q g - total gate charge (nc) v gs 0.0 0.2 0.4 0.6 0.8 1.0 1.2 t j = 150 c t j =25 c 20 1 v sd - source-to-drain voltage (v) - source current (a) i s 10 capacitance on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage 0 100 200 300 400 500 600 700 800 048121620 v ds - drain-to-source voltage (v) c rss c oss c iss c - capacitance (pf) 0.6 0.8 1.0 1.2 1.4 1.6 - 50 - 25 0 25 50 75 100 125 150 v gs =4.5v i d =4.4a t j - junction temperature ( c ) r ds(on) - on-resistance (normalized) 0.00 0.02 0.04 0.06 0.08 0.10 012345 i d =4.4a - on-resistance ( ) r ds(on) v gs - gate-to-source voltage (v) i d =2a
www.vishay.com 4 document number: 73074 s10-0548-rev. b, 08-mar-10 vishay siliconix si5908dc typical characteristics 25 c, unless otherwise noted threshold voltage -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a variance (v) v gs(th) t j - temperature ( c) single pulse power 0 30 50 10 20 po wer (w) time (s) 40 1 100 600 10 10 -1 10 -2 10 -4 10 -3 safe operating area 100 1 0.1 1 10 100 0.01 10 t a =25 c single p u lse -drainc u rrent (a) i d 0.1 dm limited i d(on) limited b v dss limited limited by r ds(on) * i 1 ms 100 s 10 ms 1 s 10 s 100 ms dc v ds - drain-to-source voltage (v) * v gs > minimum v gs at which r ds(on) is specified
document number: 73074 s10-0548-rev. b, 08-mar-10 www.vishay.com 5 vishay siliconix si5908dc typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. pro ducts may be manufactured at on e of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see www.vishay.com/ppg?73074 . normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 1 10 600 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized effective transient thermal impedance 1. duty cycle, d = 2. per unit base = r thja =90 c/w 3. t jm -t a =p dm z thja (t) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 110 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized effective transient thermal impedance
package information vishay siliconix document number: 71151 15-jan-04 www.vishay.com 1 1206-8 chipfet c e e 1 e d a 65 7 8 34 2 1 4 l 5678 4321 4 s b 2x 0.10/0.13 r backside view x notes: 1. all dimensions are in millimeaters. 2. mold gate burrs shall not exceed 0.13 mm per side. 3. leadframe to molded body offset is horizontal and vertical shall not exceed 0.08 mm. 4. dimensions exclusive of mold gate burrs. 5. no mold flash allowed on the top and bottom lead surface. detail x c1 millimeters inches dim min nom max min nom max a 1.00 ? 1.10 0.039 ? 0.043 b 0.25 0.30 0.35 0.010 0.012 0.014 c 0.1 0.15 0.20 0.004 0.006 0.008 c1 0 ? 0.038 0 ? 0.0015 d 2.95 3.05 3.10 0.116 0.120 0.122 e 1.825 1.90 1.975 0.072 0.075 0.078 e 1 1.55 1.65 1.70 0.061 0.065 0.067 e 0.65 bsc 0.0256 bsc l 0.28 ? 0.42 0.011 ? 0.017 s 0.55 bsc 0.022 bsc 5 nom 5 nom ecn: c-03528?rev. f, 19-jan-04 dwg: 5547
an812 vishay siliconix document number: 71127 12-dec-03 www.vishay.com 1 dual-channel 1206-8 chipfet power mosfet recommended pad pattern and thermal performance introduction new vishay siliconix chipfets in the leadless 1206-8 package feature the same outline as popular 1206-8 resistors and capacitors but provide all the performance of true power semiconductor devices. the 1206-8 chipfet has the same footprint as the body of the little foot tsop-6, and can be thought of as a leadless tsop-6 for purposes of visualizing board area, but its thermal performance bears comparison with the much larger so-8. this technical note discusses the dual chipfet 1206-8 pin-out, package outline, pad patterns, evaluation board layout, and thermal performance. pin-out figure 1 shows the pin-out description and pin 1 identification for the dual-channel 1206-8 chipfet device. the pin-out is similar to the tsop-6 configuration, with two additional drain pins to enhance power dissipation and thus thermal performance. the legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary. figure 1. dual 1206-8 chipfet s 1 g 1 s 2 d 1 d 1 d 2 g 2 d 2 for package dimensions see the 1206-8 chipfet package outline drawing ( http://www.vishay.com/doc?71151 ). basic pad patterns the basic pad layout with dimensions is shown in application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ). this is sufficient for low power dissipation mosfet applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. figure 2. footprint with copper spreading 80 mil 43 mil 10 mil 26 mil 18 mil 25 mil the pad pattern with copper spreading shown in figure 2 improves the thermal area of the drain connections (pins 5 and 6, pins 7 and 8) while remaining within the confines of the basic footprint. the drain copper area is 0.0019 sq. in. or 1.22 sq. mm. this will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the dual device. the addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. an example of this method is implemented on the vishay siliconix evaluation board described in the next section (figure 3). the vishay siliconix evaluation board for the dual 1206-8 the dual chipfet 1206-08 evaluation board measures 0.6 in by 0.5 in. its copper pad pattern consists of an increased pad area around each of the two drain leads on the top-side? approximately 0.0246 sq. in. or 15.87 sq. mm?and vias added through to the underside of the board, again with a maximized copper pad area of approximately the board-size dimensions, split into two for each of the drains. the outer package outline is for the 8-pin dip, which will allow test sockets to be used to assist in testing. the thermal performance of the 1206-8 on this board has been measured with the results following on the next page. the testing included comparison with the minimum recommended footprint on the evaluation board-size pcb and the industry standard one-inch square fr4 pcb with copper on both sides of the board.
an812 vishay siliconix www.vishay.com 2 document number: 71127 12-dec-03 front of board back of board figure 3. vishay.com chipfet thermal performance junction-to-foot thermal resistance (the package performance) thermal performance for the 1206-8 chipfet measured as junction-to-foot thermal resistance is 30 c/w typical, 40 c/w maximum for the dual device. the ?foot? is the drain lead of the device as it connects with the body. this is identical to the dual so-8 package r jf performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area. junction-to-ambient thermal resistance (dependent on pcb size) the typical r ja for the dual-channel 1206-8 chipfet is 90 c/w steady state, identical to the so-8. maximum ratings are 110 c/w for both the 1206-8 and the so-8. both packages have comparable thermal performance on the 1? square pcb footprint with the 1206-8 dual package having a quarter of the body area, a significant factor when considering board area. testing to aid comparison further, figure 4 illustrates chipfet 1206-8 dual thermal performance on two different board sizes and three different pad patterns.the results display the thermal performance out to steady state and produce a graphic account on how an increased copper pad area for the drain connections can enhance thermal performance. the measured steady state values of r ja for the dual 1206-8 chipfet are : 1) minimum recommended pad pattern (see figure 2) on the evaluation board size of 0.5 in x 0.6 in. 185 c/w 2) the evaluation board with the pad pattern described on figure 3. 128 c/w 3) industry standard 1? square pcb with maximum copper both sides. 90 c/w the results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. in this example, a 57 c/w reduction was achieved without having to increase the size of the board. if increasing board size is an option, a further 38 c/w reduction was obtained by maximizing the copper from the drain on the larger 1? square pcb. time (secs) figure 4. dual 1206-8 chipfet thermal resistance (c/w) 0 1 200 40 80 100 1000 120 10 10 -1 10 -2 10 -3 10 -4 10 -5 1? square pcb dual evb min. footprint 160 summary the thermal results for the dual-channel 1206-8 chipfet package display identical power dissipation performance to the so-8 with a footprint reduction of 80%. careful design of the package has allowed for this performance to be achieved. the short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the tsop-6 body size. associated document 1206-8 chipfet single thermal performance, an811, (http://www.vishay.com/doc?71126) .
application note 826 vishay siliconix www.vishay.com document number: 72593 2 revision: 21-jan-08 application note recommended minimum pads for 1206-8 chipfet ? 0.080 (2.032) recommended mi nimum pads dimensions in inches/(mm) 0.093 (2.357) 0.036 (0.914) 0.022 (0.559) 0.026 (0.650) 0.016 (0.406) 0.010 (0.244) return to index return to index
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